? semiconductor components industries, llc, 2001 september, 2001 rev. 3 1 publication order number: mc74hc4020a/d mc74hc4020a 14-stage binary ripple counter highperformance silicongate cmos the mc74c4020a is identical in pinout to the standard cmos mc14020b. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device consists of 14 masterslave flipflops with 12 stages brought out to pins. the output of each flipflop feeds the next and the frequency at each output is half of that of the preceding one. reset is asynchronous and activehigh. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and may have to be gated with the clock of the hc4020a for some designs. ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2 to 6 v ? low input current: 1 m a ? high noise immunity characteristic of cmos devices ? in compliance with jedec standard no. 7a requirements ? chip complexity: 398 fets or 99.5 equivalent gates logic diagram q1 9 q4 7 q5 5 q6 4 q7 6 q8 13 q9 12 q10 14 q11 15 q12 1 q13 2 q14 3 clock 10 reset 11 pin 16 = v cc pin 8 = gnd 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 q11 q10 q8 q9 reset clock q1 q12 q13 q14 q6 q5 q7 q4 gnd pinout: 16lead plastic package (top view) http://onsemi.com so16 d suffix case 751b tssop16 dt suffix case 948f 1 16 pdip16 n suffix case 648 1 16 1 16 marking diagrams 1 16 mc74hc4020an awlyyww 1 16 hc4020a awlyww a = assembly location wl = wafer lot yy = year ww = work week hc40 20a alyw 1 16 device package shipping ordering information mc74hc4020an pdip16 2000 / box mc74hc4020ad soic16 48 / rail mc74hc4020adr2 soic16 2500 / reel mc74hc4020adt tssop16 96 / rail mc74hc4020adtr2 tssop16 2500 / reel function table clock reset output state x l l h no charge advance to next state all outputs are low
mc74hc4020a http://onsemi.com 2 ??????????????????????? ??????????????????????? maximum ratings* ???? ???? symbol ?????????????? ?????????????? parameter ????? ????? value ??? ??? unit ???? ???? v cc ?????????????? ?????????????? dc supply voltage (referenced to gnd) ????? ????? 0.5 to + 7.0 ??? ??? v ???? ???? v in ?????????????? ?????????????? dc input voltage (referenced to gnd) ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? v out ?????????????? ?????????????? dc output voltage (referenced to gnd) ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? i in ?????????????? ?????????????? dc input current, per pin ????? ????? 20 ??? ??? ma ???? ???? i out ?????????????? ?????????????? dc output current, per pin ????? ????? 25 ??? ??? ma ???? ???? i cc ?????????????? ?????????????? dc supply current, v cc and gnd pins ????? ????? 50 ??? ??? ma ???? ? ?? ? ???? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air plastic dip2 soic package2 tssop package2 ????? ? ??? ? ????? 750 500 450 ??? ? ? ? ??? mw ???? ???? t stg ?????????????? ?????????????? storage temperature range ????? ????? 65 to + 150 ??? ??? c ???? ? ?? ? ???? t l ?????????????? ? ???????????? ? ?????????????? lead temperature, 1 mm from case for 10 seconds plastic dip, soic or tssop package ????? ? ??? ? ????? 260 ??? ? ? ? ??? c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c soic package: 7 mw/ c from 65 to 125 c tssop package: 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the on semiconductor highspeed cmos data book (dl129/d). recommended operating conditions ???? ???? symbol ??????????????? ??????????????? parameter ??? ??? min ?? ?? max ??? ??? unit ???? ???? v cc ??????????????? ??????????????? dc supply voltage (referenced to gnd) ??? ??? 2.0 ?? ?? 6.0 ??? ??? v ???? ???? v in , v out ??????????????? ??????????????? dc input voltage, output voltage (referenced to gnd) ??? ??? 0 ?? ?? v cc ??? ??? v ???? ???? t a ??????????????? ??????????????? operating temperature range, all package types ??? ??? 55 ?? ?? + 125 ??? ??? c ???? ? ?? ? ? ?? ? ???? t r , t f ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? input rise/fall time v cc = 2.0 v (figure 1) v cc = 3.0 v v cc = 4.5 v v cc = 6.0 v ??? ? ? ? ? ? ? ??? 0 0 0 0 ?? ?? ?? ?? 1000 600 500 400 ??? ? ? ? ? ? ? ??? ns dc characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter condition v cc v 55 to 25 c 85 c 125 c unit v ih minimum highlevel input voltage v out = 0.1v or v cc 0.1v |i out | 20 m a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum lowlevel input voltage v out = 0.1v or v cc 0.1v |i out | 20 m a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v oh minimum highlevel output voltage v in = v ih or v il |i out | 20 m a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il |i out | 2.4ma |i out | 4.0ma |i out | 5.2ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum lowlevel output voltage v in = v ih or v il |i out | 20 m a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4ma |i out | 4.0ma |i out | 5.2ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc4020a http://onsemi.com 3 dc characteristics (voltages referenced to gnd) symbol unit guaranteed limit v cc v condition parameter symbol unit 125 c 85 c 55 to 25 c v cc v condition parameter i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 m a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 m a 6.0 4 40 160 m a note: information on typical parametric values can be found in chapter 2 of the on semiconductor highspeed cmos data book (dl129/d). ac characteristics (c l = 50 pf, input t r = t f = 6 ns) v cc guaranteed limit symbol parameter v cc v 55 to 25 c 85 c 125 c unit f max maximum clock frequency (50% duty cycle) (figures 1 and 4) 2.0 3.0 4.5 6.0 10 15 30 50 9.0 14 28 50 8.0 12 25 40 mhz t plh , t phl maximum propagation delay, clock to q1* (figures 1 and 4) 2.0 3.0 4.5 6.0 96 63 31 25 106 71 36 30 115 88 40 35 ns t phl maximum propagation delay, reset to any q (figures 2 and 4) 2.0 3.0 4.5 6.0 45 30 30 26 52 36 35 32 65 40 40 35 ns t plh , t phl maximum propagation delay, qn to qn+1 (figures 3 and 4) 2.0 3.0 4.5 6.0 69 40 17 14 80 45 21 15 90 50 28 22 ns t tlh , t thl maximum output transition time, any output (figures 1 and 4) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns c in maximum input capacitance 10 10 10 pf note: for propagation delays with loads other than 50 pf, and information on typical parametric values, see chapter 2 of the on semiconductor highspeed cmos data book (dl129/d). * for t a = 25 c and c l = 50 pf, typical propagation delay from clock to other q outputs may be calculated with the following equations: v cc = 2.0 v: t p = [93.7 + 59.3 (n1)] ns v cc = 4.5 v: t p = [30.25 + 14.6 (n1)] ns v cc = 3.0 v: t p = [61.5 + 34.4 (n1)] ns v cc = 6.0 v: t p = [24.4 + 12 (n1)] ns typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (per package)* 38 pf * used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the on semiconductor highspeed cmos data book (dl129/d).
mc74hc4020a http://onsemi.com 4 timing requirements (input t r = t f = 6 ns) v cc guaranteed limit symbol parameter v cc v 55 to 25 c 85 c 125 c unit t rec minimum recovery time, reset inactive to clock (figure 2) 2.0 3.0 4.5 6.0 30 20 5 4 40 25 8 6 50 30 12 9 ns t w minimum pulse width, clock (figure 1) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns t w minimum pulse width, reset (figure 2) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns t r , t f maximum input rise and fall times (figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns note: information on typical parametric values can be found in chapter 2 of the on semiconductor highspeed cmos data book (dl129/d). pin descriptions inputs clock (pin 10) negativeedge triggering clock input. a hightolow transition on this input advances the state of the counter. reset (pin 11) activehigh reset. a high level applied to this input asynchronously resets the counter to its zero state, thus forcing all q outputs low. outputs q1, q4eq14 (pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3) activehigh outputs. each qn output divides the clock input frequency by 2 n . switching waveforms t f clock q1 v cc gnd 90% 50% 10% t r t w 90% 50% 10% t phl 1/f max t plh t tlh t thl clock v cc gnd t w t rec 50% figure 1. figure 2. reset v cc gnd 50% any q 50% t phl
mc74hc4020a http://onsemi.com 5 switching waveforms (continued) 50% qn v cc gnd 50% qn+1 c l * *includes all probe and jig capacitance test point device under test output figure 3. figure 4. test circuit t plh t phl figure 5. expanded logic diagram clock 10 c c r reset 11 q q c c r q q q1 9 c c q q c c q q c c q q c c q q4 7 q5 5 q12 1 q13 2 q14 3 q6 = pin 4 q7 = pin 6 q8 = pin 13 q9 = pin 12 q10 = pin 14 q11 = pin 15 v cc = pin 16 gnd = pin 8
mc74hc4020a http://onsemi.com 6 clock reset q4 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 q5 q6 q7 q8 q9 q10 q12 q13 q14 figure 6. timing diagram applications information timebase generator a 60hz sinewave obtained through a 1.0 megohm resistor connected directly to a standard 120 vac power line is applied to the input of the mc54/74hc14a, schmitt-trigger inverter. the hc14a squaresup the input waveform and feeds the hc4020a. selecting outputs q5, q10, q11, and q12 causes a reset every 3600 clocks. the hc20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. the resulting output frequency is 1.0 pulse/minute. hc4020a figure 7. timebase generator clock q5 q10 q11 q12 v cc 13 12 10 9 1 2 4 5 8 1/2 hc20 1/2 hc20 6 1/6 of hc14a 20pf 1.0m 1.0 pulse/minute output v cc 120vac 60hz note: ground must be isolated by a transformer or optoisolator for safety reasons.
mc74hc4020a http://onsemi.com 7 package dimensions pdip16 n suffix case 64808 issue r min min max max inches millimeters dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc a b 18 9 16 f h g d 16 pl s c t seating plane k j m l ta 0.25 (0.010) m m 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m soic16 d suffix case 751b05 issue j
mc74hc4020a http://onsemi.com 8 package dimensions tssop16 dt suffix case 948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74hc4020a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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